The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to decoding bank addresses during a setup time for row and column addresses in multiple-bank semiconductor memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
In synchronous memory devices, address and control inputs are referenced to a system clock with the same setup and hold times to insure that the information is valid at the proper time and available for a sufficient amount of time. As memory architectures increase in size, more complex addressing schemes are required to better manage the addressable memory locations. One such addressing scheme is to divide the memory array into multiple memory banks, with one or more address bits, or address input signals, determining which memory bank to address, and the remaining address bits, or address input signals, determining the row(s) and column(s) within a memory bank. However, complex addressing schemes make coordinating the decoding of address input signals more difficult as decoding of certain address input signals may be required before others.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods and circuits for decoding addresses in high-performance memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The various embodiments of the invention include methods and apparatus for decoding an externally-applied address in a synchronous memory device arranged to decode a first portion of the address during a setup time and to decode a second portion of the address following the setup time. The first portion of the address may be indicative of a bank address of a multiple-bank memory device. The second portion of the address may be indicative of row and column addresses within a bank of the multiple-bank memory device.
For one embodiment, the invention provides an address input buffer stage. The address input buffer stage includes at least one address input for receiving at least one address input signal of an externally-applied address, a buffer coupled to each address input, an address decoder having each input coupled to a buffer, and latches coupled to each output of the address decoder through selective coupling devices.
For another embodiment, the invention provides an address input buffer stage. The address input buffer stage includes at least two buffers, each buffer coupled to an address input for receiving address input signals of an externally-applied address, at least three latches, and an address decoder coupled between the buffers and the latches.
For yet another embodiment, the invention provides a method of decoding an externally-applied address for a memory device. The method includes decoding at least a portion of address input signals of the externally-applied address prior to latching the portion of address input signals in the memory device. For still another embodiment, the method includes decoding at least a portion of address input signals of the externally-applied address without latching the portion of address input signals in the memory device.
For a further embodiment, the invention provides a method of accessing a target memory cell in a memory device having at least two memory banks. The method includes buffering at least one bank address input signal and remaining address input signals of an externally-applied address in the memory device, thereby generating at least one buffered bank address input signal and buffered remaining address input signals. The externally-applied address is indicative of a location of the target memory cell. The method further includes decoding a bank address from the at least one buffered bank address input signal prior to latching the at least one bank address input signal in the memory device, thereby generating a decoded bank address indicative of a target memory bank containing the target memory cell, delaying the buffered remaining address input signals while decoding the bank address, and latching the decoded bank address and the buffered remaining address input signals in the memory device at approximately the same time. The method still further includes selecting a row decoder circuit from a plurality of row decoder circuits in response to the decoded bank address, selecting a column decoder circuit from a plurality of column decoder circuits in response to the decoded bank address, decoding at least a portion of the buffered remaining address input signals using the selected row decoder circuit, thereby producing a decoded row address, and decoding at least a portion of the buffered remaining address input signals using the selected column decoder circuit, thereby producing a decoded column address. The method still further includes accessing the target memory cell in response to the decoded row address and the decoded column address.
For yet another embodiment, the invention provides a synchronous flash memory device. The memory device includes a plurality of address inputs having a first portion and a second portion, at least two memory banks containing arrays of non-volatile flash memory cells arranged in addressable rows and columns, a row decoder having at least two row decoder circuits coupled to the at least two memory banks, a column decoder having at least two column decoder circuits coupled to the at least two memory banks, and an address bus coupled to the row decoder and the column decoder. The memory device further includes a first address input buffer stage for providing a first decoded address to select a row decoder circuit from the row decoder and a column decoder circuit from the column decoder. The first address input buffer stage includes at least one buffer, wherein each buffer is coupled to one address input of the first portion of address inputs in a one-to-one relationship, an address decoder having at least one input and at least two outputs for providing the first decoded address, wherein each input of the address decoder is coupled to one of the buffers in a one-to-one relationship, and at least two latches, wherein an input of each latch is coupled to one of the outputs of the address decoder in a one-to-one relationship through a selective coupling device, further wherein an output of each latch is coupled to the row decoder and the column decoder. The memory device still further includes at least two second address input buffer stages coupled to the address bus for providing address input signals from the second portion of the address inputs to a selected row decoder circuit of the row decoder and a selected column decoder circuit of the column decoder, and a command execution logic for receiving at least a system clock input signal, for generating an internal clock signal in response to the system clock input signal, and for generating control signals to control operations performed by the row decoder, the column decoder, the first address input buffer stage and each second address input buffer stage synchronized to the internal clock signal.
The invention further provides methods and apparatus of varying scope.